Home > ADCOM 2019 > An Interview with Prof. V. Ramgopal Rao: Making Sense of the Future of Electronics

An Interview with Prof. V. Ramgopal Rao: Making Sense of the Future of Electronics

Prof. V. Ramgopal Rao

Prof. V. Ramgopal Rao, is leading investigations into the science and engineering of nanoscale electronic devices. His seminal work on FinFeT transistors using bulk CMOS instead of Silicon on Insulator (SoI) technology has led to further miniaturization of processors beyond 7 nm. Prof. Rao was conferred the ACCS-CDAC Foundation Award for 2019 at ADCOM 2019. Prashanth Hebbar from ACC Journal caught up with Prof. Rao and discussed on a range of subjects close to his heart. An excerpt from the discussion follows.

Prashanth Hebbar (PH): How did you really get interested in MOSFETs, when you entered the field probably it was so wide?

Prof. V. Ramgopal Rao (RGR): My Ph.D. was on MOSFETs (Metal Oxide Field Effect Transistor). In Germany I did my Ph.D. on vertical MOSFETs while everybody was working on lateral kind of MOSFETs. During 1995 – 1997 timeframe, I was working on vertical MOSFETs which was a completely new area at that time. We were using lots of new approaches for the future generation of MOSFETs. While the world was working with 0.5 and 0.75 microns, we were working on sub – 0.1 microns. So that was my introduction to MOSFETs.

PH: I think one of your most seminal papers is the ‘Drain Extended Field Effect Transistor’ which paved the way for the sub-20 nm. Where and how did you get that motivation to work on?

RGR: Let’s look at what happens in the industry today. We want to integrate all functions on a single chip, but the technology usually is scaled down kind of a version which supports 1 Volt, 0.8 Volt kind of supply voltages.

But then on the same chip they want to have devices which also can work with 10, 12 Volts. The question is, how can a MOSFET which works with 1 Volt also work with 12 Volts which are all on the same dye. You cannot have a process which is very divergent because it will add to the cost of the entire chip.

So, the whole game was or the game still is how do you integrate different types of functionalities on the same chip that is a system on chip, say, the entire mobile phone on a single chip. If you look at the digital cameras, they are so pervasive because the entire digital camera is on one single chip. Because of that, you can put it on any device, be it a mobile phone or any other device.

If you can have the entire mobile phone on a single chip, then you can have mobile phones practically everywhere. But to do that is a lot more complex because mobile on a chip is not just about logic; there is lot of analog processing and these days you want to connect to USB drives, and you want to do many more things with the mobile.  That calls for devices which work under very diverse conditions but then you cannot have a different process for every different device.

With the existing standard CMOS (Composite Metal Oxide Semiconductor) we cannot integrate so many processes in a single chip. If you want to use the conventional core technologies with a 12 Volts kind of a supply, then the drain extended MOS devices is promising because by extending the drain it can absorb higher voltage so we can apply more voltages.

That is how the whole thing began and we introduced very novel concepts to the devices. [At that time] people were aware of the drain extended MOS devices, but we introduced a shallow trench isolation (STI) and optimized the devices. We tried to understand the reliability of these devices which used shallow trench isolation; design it and integrate them into existing CMOS flow. That is where Intel’s contribution was as they were able to test these devices that we were designing. Intel was having a lot of interest in the mobile communication at one point of time and it acquired a group in Infineon with whom I was working.

PH: Did you originally come up with the idea of STI or was there a cross domain team working on this?

RGR: It was a group effort. All the patents are joint patents. We filed almost 20 patents with Intel and many of them were joint patents. There are students involved as well. We were innovating and coming up with ideas. All these patents that we have filed are essentially the ideas that we were able to generate, and which were tested and verified by Intel.

PH: Now moving over to FinFETs (Fin shaped Field Effect Transistor), you had some seminal contributions to make there as well. There is a perception that FinFETs are expensive. I think Samsung took some initiative and they are moving onto another version of FinFETs, so what is your viewpoint?

RGR: No, FinFETs are already there now. Every mobile phone, every chip that you see today that are 10 nanometer and 7 nanometer processors, they are all based on FinFETs. There are no conventional MOSFETs anyway. Our innovation was that while FinFETs often use SOI kind of processors which makes it easier in terms of processing, we tried to optimize the FinFETs for bulk applications.

That was a major contribution from our group. We tried to understand, optimize and then give directions to how these FinFETs instead of being on the SOI which is a very costly process can be integrated on bulk. We studied what sort of effects will come in and how can we alleviate those challenges.

We introduced lots of different concepts into the bulk FinFETs and that is a process now which everybody uses. In SOI it’s very simple but it’s expensive. In bulk it becomes a bit complex and there are lots of physical effects that take place which are unwanted. Now, the question is how to integrate on the bulk process yet contain all of those effects that you see. That is where we introduced new concepts into FinFETs. We have patents for them as well.

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